The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, this scaling down process has placed higher requirements on the flatness of a wafer surface because relatively small non-flatness (e.g., a dip or a bump) in the wafer surface might cause layer misalignment or even circuit defects. As wafer size gets larger (e.g., from 200 mm to 300 mm), the issue of local non-flatness becomes more prominent. Existing semiconductor fabrication equipment and methods do not seem to address this issue satisfactorily. Accordingly, improvements in this area are desired.